This invention relates generally to integrated circuits, and more particularly, to a circuit for creating a clock signal with a controllable pulse width.
Dynamic logic circuits are often used in modern integrated circuits. One problem that can arise with dynamic circuits, however, is the decay, or discharge of a non-driven node over time. This can cause errors. To prevent these types of errors, it may be desirable to shorten one phase of a clock that regulates the timing of some dynamic circuits. By shortening this phase, the amount of time a node spends non-driven may be shortened without affecting the overall average clock cycle time, which may be critical to system performance. Accordingly, there is a need in the art for a circuit that can control the pulse width of a clock.
Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.